1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof, and more particularly, to a semiconductor device having a multilayer interconnection structure and manufacturing method thereof.
2. Description of the Related Art
In general, multilayered interconnection technology employs three-dimensional integrated circuits to more effectively utilize the surface area of the integrated circuits. Highly integrated memory devices having a large capacity equal to or greater than 1 gigabyte, for example, a dynamic random access memory (DRAM) device, can be designed by employing the multilayered interconnection technology.
In multilayer interconnections, active devices and interconnections have a structure in which layers are stacked, and each layer is connected by an interlevel, or interlayer, connection path such as a “plug” or “stud”. Also, a “landing pad” or “tab” for assisting the alignment of the plug is formed on an underlying layer to serve as a target for a plug. Further, the landing pad is connected to an underlying circuit or interconnection, and its surface area is formed to be larger than that of the underlying circuit or interconnection. This results in a larger tolerance of the target for the plug. However, a conventional landing pad or tap assists the alignment of the plug, and due to the width being larger than that of the stud (or plug), there is a high risk that a short-circuit may occur between neighboring circuit patterns. Thus, at present, instead of using the landing pad, a technology in which self-aligned metal interconnections are formed by an etch stopper has been suggested.
FIG. 1 is a sectional view of a conventional multilayer metal interconnection structure including a stud and an etch stopper, as disclosed in U.S. Pat. No. 5,891,799. Referring first to FIG. 1, a metal interconnection 102 is formed on a semiconductor substrate 100. A first interlevel dielectric (ILD) layer 104 composed of silicon dioxide (SiO2) and a first etch stopper 106 composed of silicon nitride (Si3N4) are sequentially formed on the semiconductor substrate 100 on which the metal interconnection 102 is formed. Next, lower stud holes 108a and 108b are formed by patterning the first etch stopper 106 and the first ILD layer 104 to expose the metal interconnection 102 and the semiconductor substrate 100. Next, the lower stud holes 108a and 108b are filled with a metal material to form lower studs 110a and 110b. A second ILD layer 112 and a second etch stopper 114 are sequentially formed on the resultant of the semiconductor substrate 100 on which the lower studs 110a and 110b are formed. Next, upper stud holes 116a and 116b are formed by etching the second etch stopper 114 and the second ILD layer 112 to expose the lower studs 110a and 110b. Here, during an etching process for forming the upper stud holes 116a and 116b, the first etch stopper 106 serves as an etching reference. Next, upper studs 118a and 118b are formed in the upper stud holes 116a and 116b. 
However, the following problems arise in a conventional multilayer interconnection structure. First, in the mentioned prior art, a landing pad is not used. Thus, even though the first etch stopper 106 is used, there is a high risk that misalignment between the lower studs 110a, 110b and the upper studs 118a, 118b may occur. Meanwhile, when the landing pad is used, as described above, the distance between patterns decreases. Thus, a short-circuit can readily occur between neighboring conductive patterns.
Furthermore, a bit line of the DRAM is often used as a local interconnection on a peripheral region on which a sense amplifier is formed. In particular, since circuit layers are very densely arranged on the peripheral region, it is not easy to secure a safe distance between patterns in the horizontal direction that are formed on the same level.
Also, since the first and second etch stoppers 106 and 114 composed of silicon nitride (Si3N4) are formed on the entire resultant of the semiconductor substrate 100, excessive stress causing circuit distortion occurs in the ILD layers. Furthermore, the first and second etch stoppers 106 and 114 prevent impurities such as carbon (C), fluorine (F), and chlorine (Cl), which are contained in the ILD layers, from being outgassed during a subsequent high temperature heating process. Also, the remaining etch stoppers 106 and 114 disturb the introduction of H2 and O2 during a thermal process for reducing dangling bonds between the semiconductor substrate 100 and a gate insulating layer (not shown). As a result, the adhesion characteristics between the semiconductor substrate 100 and the gate insulating layer are adversely affected.